Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system. The design flow typically starts with a specification for a new circuit, which can be transformed into a logical design. The logical design can model the circuit at a register transfer level (RTL), which is usually coded in a Hardware Description Language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Description Language (VHDL), System C, or the like.
The logical design typically utilizes a design hierarchy to describe the circuit in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. For example, when the circuit includes a processing system having multiple processing cores, rather than describe the entire processing system with each of the processing cores separately, i.e., in a flat representation, the logical design can describe a design unit for the processing core, which can be linked to multiple locations in a design unit for a processing system.
A common technique for linking or interfacing the various design units is to modify the logical design with the addition of code statements, so that once design units have been compiled, they can be interconnected during elaboration based on the code statements. For example, a higher-level design unit of the logical design can be modified to include an instantiation statement, so that once design units have been compiled, the higher-level design unit can instantiate a lower-level design unit in response to execution of the compiled instantiation statement during elaboration.
On many occasions, however, the inclusion of an instantiation statement in the higher-level design unit becomes impossible, as the higher-level design unit was purchased already-compiled with no access to the source code or the design units may be written in different languages. While other design unit linking techniques exist, such as the use of System Verilog bind commands, System C Control and Observe commands, System C Verification Connect commands, System C Direct Programming Interface commands, or the like, their utilization relies heavily on expertise of design engineers.
Even when a design team includes an engineer having the expertise to link the design units with one of these techniques, the modification of the logical design with code statements can introduce implicit hierarchies and possibly dummy hierarchies, which can complicate functional verification operations, coverage recordation, functional verification reporting, or the like. After functional verification, the modified logical design can be provided to one or more downstream tools, such as a place and route tool, which can consider the code statements and their associated hierarchies as portions of the logical design, complicating operation of these downstream tools.